JEDEC JESD8-18A

JEDEC JESD8-18A

Click here to purchase
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s.

Product Details

Published:
03/01/2008
Number of Pages:
68
File Size:
1 file , 3.6 MB

You may also like

JEDEC JEB 5-A (R1984)

JEDEC JEB 5-A (R1984)

METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITSstandard by JEDEC Solid State Technology Association, 01/01/1970

JEDEC JEP114.01

JEDEC JEP114.01

GUIDELINES FOR PARTICLE IMPACT NOISE DETECTION (PIND) TESTING, OPERATOR TRAINING, AND CERTIFICATIONstandard by JEDEC Solid State Technology Association, 10/01/2007

JEDEC JEP128

JEDEC JEP128

GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTINGstandard by JEDEC Solid State Technology Association, 11/01/1996

JEDEC JEP122H

JEDEC JEP122H

Failure Mechanisms and Models for Semiconductor Devicesstandard by JEDEC Solid State Technology Association, 09/01/2016

Back to Top