JEDEC JESD75

JEDEC JESD75

Click here to purchase
The purpose of this standard is to provide a pinout standard for dual-die 32-bit logic devices offered in a 96- and 144-ball grid array package for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease use. This standard defines device output for 32-bit wide buffer, driver and transceiver functions. This pinout specifically applies to the conversion of DIP-packaged 16-bit logic devices to LFBGA-packaged dual-die 32-bit logic devices.

Product Details

Published:
11/01/1999
Number of Pages:
7
File Size:
1 file , 98 KB

You may also like

JEDEC JEP128

JEDEC JEP128

GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTINGstandard by JEDEC Solid State Technology Association, 11/01/1996

JEDEC JEP122H

JEDEC JEP122H

Failure Mechanisms and Models for Semiconductor Devicesstandard by JEDEC Solid State Technology Association, 09/01/2016

JEDEC JEB 5-A (R1984)

JEDEC JEB 5-A (R1984)

METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITSstandard by JEDEC Solid State Technology Association, 01/01/1970

JEDEC JEP114.01

JEDEC JEP114.01

GUIDELINES FOR PARTICLE IMPACT NOISE DETECTION (PIND) TESTING, OPERATOR TRAINING, AND CERTIFICATIONstandard by JEDEC Solid State Technology Association, 10/01/2007

Back to Top