JEDEC JESD71

JEDEC JESD71

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STAPL is a vendor- and platform-independent language for programming and testing devices via the IEEE standard 1149.1 interface, commonly known as JTAG. STAPL enables programming of designs into programmable logic devices (PLDs) offered by a variety of PLD vendors. STAPL is also suitable for testing 1149.1-compliant devices.

Product Details

Published:
08/01/1999
Number of Pages:
48
File Size:
1 file , 400 KB

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