JEDEC JESD217.01

JEDEC JESD217.01

Click here to purchase
As ball grid array component pitch continues to decrease, the need to characterize solder voidinghas become more significant. Solder void manifestation (type and/or sizes) has been used todetermine process capability as a means of quality assurance during process transfer, and asindicators of process stability from in-line manufacturing monitors. This document describeshow to characterize voids in solder spheres in ball grid array packages prior to surface-mount(SMT) reflow soldering.

Product Details

Published:
10/01/2016
Number of Pages:
46
File Size:
1 file , 1.7 MB

You may also like

JEDEC JEP128

JEDEC JEP128

GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTINGstandard by JEDEC Solid State Technology Association, 11/01/1996

JEDEC JEP122H

JEDEC JEP122H

Failure Mechanisms and Models for Semiconductor Devicesstandard by JEDEC Solid State Technology Association, 09/01/2016

JEDEC JEB 5-A (R1984)

JEDEC JEB 5-A (R1984)

METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITSstandard by JEDEC Solid State Technology Association, 01/01/1970

JEDEC JEP114.01

JEDEC JEP114.01

GUIDELINES FOR PARTICLE IMPACT NOISE DETECTION (PIND) TESTING, OPERATOR TRAINING, AND CERTIFICATIONstandard by JEDEC Solid State Technology Association, 10/01/2007

Back to Top