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This standard defines a minimum set of macro cell standards for CMOS gate arrays. A total of 41 macro cell types are addressed, all of which are commonly used by gate array designers to implement Application Specific Integrated Circuits.
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GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTINGstandard by JEDEC Solid State Technology Association, 11/01/1996
Failure Mechanisms and Models for Semiconductor Devicesstandard by JEDEC Solid State Technology Association, 09/01/2016