JEDEC JEP171

JEDEC JEP171

Click here to purchase
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5.

This document provides the test methodology details on:

  • CK and WCK Timings: tCK, tWCK, tCH/tCL, tWCKH/tWCKL, CK TJ/RJrms, CK and WCK Jitter
  • CK and WCK Input Operating Conditions: VIXCK, VIXWCK, VIDCK(ac), VIDWCK(ac), VIDCK(dc),VIDWCK(dc), CKslew, and WCKslew
  • Data Input Timings: tDIVW, tDIPW

Note: The procedures described in this document are intended to provide information about the tests that will be used in JEDEC GDDR5 recommended measurement parameter. This testing is not a replacement for an exhaustive test validation plan.

Product Details

Published:
2014
Number of Pages:
34
File Size:
1 file , 3 MB

You may also like

JEDEC JEB 5-A (R1984)

JEDEC JEB 5-A (R1984)

METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITSstandard by JEDEC Solid State Technology Association, 01/01/1970

JEDEC JEP114.01

JEDEC JEP114.01

GUIDELINES FOR PARTICLE IMPACT NOISE DETECTION (PIND) TESTING, OPERATOR TRAINING, AND CERTIFICATIONstandard by JEDEC Solid State Technology Association, 10/01/2007

JEDEC JEP128

JEDEC JEP128

GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTINGstandard by JEDEC Solid State Technology Association, 11/01/1996

JEDEC JEP122H

JEDEC JEP122H

Failure Mechanisms and Models for Semiconductor Devicesstandard by JEDEC Solid State Technology Association, 09/01/2016

Back to Top