ADDENDUM No. 4 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS (DELTA BASE-EMITTER VOLTAGE METHOD)Amendment by JEDEC Solid State Technology Association,

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 08/01/2018

AIR-CONVECTION-COOLED, LIFE TEST ENVIRONMENT FOR LEAD-MOUNTED SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 03/01/1966

IC LATCH-UP TESTstandard by JEDEC Solid State Technology Association, 09/01/2010

GUIDELINE FOR RESIDUAL GAS ANALYSIS (RGA) FOR MICROELECTRONIC PACKAGESstandard by JEDEC Solid State Technology Association, 07/01/2002

TEMPERATURE, BIAS, AND OPERATING LIFEstandard by JEDEC Solid State Technology Association, 06/01/2005

Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA)standard by JEDEC Solid State Technology Association, 01/01/2013

STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATUREstandard by JEDEC Solid State Technology Association, 02/01/1998

REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATIONstandard by JEDEC Solid State Technology Association, 10/01/2006

ISOTHERMAL ELECTROMIGRATION TEST PROCEDUREstandard by JEDEC Solid State Technology Association, 10/01/2007

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATIONstandard by JEDEC Solid State Technology Association, 03/01/2012

THERMAL SHOCKstandard by JEDEC Solid State Technology Association, 11/01/2016