DDR4 Protocol Checksstandard by JEDEC Solid State Technology Association, 07/01/2017

ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHODAmendment by JEDEC Solid State Technology Association, 01/01/1991

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATIONstandard by JEDEC Solid State Technology Association, 03/01/2009

Lead Integritystandard by JEDEC Solid State Technology Association, 02/01/2018

SPECIALITY DDR2-1066 SDRAMstandard by JEDEC Solid State Technology Association, 11/01/2007

Characterization of Interfacial Adhesion in Semiconductor Packagesstandard by JEDEC Solid State Technology Association, 04/01/2013

AVALANCHE BREAKDOWN DIODE (ABD) TRANSIENT VOLTAGE SUPPRESSORSstandard by JEDEC Solid State Technology Association, 12/01/2007

RANGES AND CONDITIONS FOR SPECIFYING BETA FOR LOW POWER, AUDIO FREQUENCY TRANSISTORS FOR ENTERTAINMENT SERVICEstandard by JEDEC Solid State Technology Association, 01/01/1965

Potential Failure Mode and Effects Analysis (FMEA)standard by JEDEC Solid State Technology Association, 08/01/2018

SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)standard by JEDEC Solid State Technology Association, 05/01/2014

GUIDELINES FOR THE MEASUREMENT OF THERMAL RESISTANCE OF GaAs FETSstandard by JEDEC Solid State Technology Association, 07/01/1988

STEADY-STATE TEMPERATURE HUMIDITY BIAS LIFE TESTstandard by JEDEC Solid State Technology Association, 03/01/2009