JEDEC JESD74A
EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTSstandard by JEDEC Solid State Technology Association, 02/01/2007
EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTSstandard by JEDEC Solid State Technology Association, 02/01/2007
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONSstandard by JEDEC Solid State
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TESTstandard by JEDEC Solid State Technology Association, 10/01/2011
IPC/JEDEC-9703: Mechanical Shock Test Guidelines for Solder Joint Reliabilitystandard by JEDEC Solid State Technology Association, 03/01/2009
MEASUREMENT OF SMALL VALUES OF TRANSISTOR CAPACITANCEstandard by JEDEC Solid State Technology Association, 07/01/1972
MULTIMEDIACARD (MMC) ELECTRICAL STANDARD, HIGH CAPACITY (MMCA, 4.2)standard by JEDEC Solid State Technology Association, 07/01/2007
COMMON FLASH INTERFACE (CFI)standard by JEDEC Solid State Technology Association, 09/01/2003
THERMAL RESISTANCE MEASUREMENTS OF CONDUCTION COOLED POWER TRANSISTORSstandard by JEDEC Solid State Technology Association, 10/01/1975
1.2 V High-Speed LVCMOS (HS_LVCMOS) Interfacestandard by JEDEC Solid State Technology Association, 09/01/2011
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONSstandard by JEDEC Solid
APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGYstandard by JEDEC Solid State Technology Association, 07/01/2008