ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR

MULTIMEDIACARD (MMC) ELECTRICAL STANDARD, HIGH CAPACITY (MMCA, 4.2)standard by JEDEC Solid State Technology Association, 07/01/2007

COMMON FLASH INTERFACE (CFI)standard by JEDEC Solid State Technology Association, 09/01/2003

Salt Atmospherestandard by JEDEC Solid State Technology Association, 04/01/2013

DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONSstandard by JEDEC Solid State

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TESTstandard by JEDEC Solid State Technology Association, 10/01/2011

IPC/JEDEC-9703: Mechanical Shock Test Guidelines for Solder Joint Reliabilitystandard by JEDEC Solid State Technology Association, 03/01/2009

MEASUREMENT OF SMALL VALUES OF TRANSISTOR CAPACITANCEstandard by JEDEC Solid State Technology Association, 07/01/1972

PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)standard by JEDEC Solid State Technology Association, 10/01/2013

GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 11/01/2016

THERMAL RESISTANCE MEASUREMENTS OF CONDUCTION COOLED POWER TRANSISTORSstandard by JEDEC Solid State Technology Association, 10/01/1975

1.2 V High-Speed LVCMOS (HS_LVCMOS) Interfacestandard by JEDEC Solid State Technology Association, 09/01/2011