3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactionsstandard by JEDEC Solid State Technology Association, 11/01/2009

DOUBLE DATA RATE (DDR) SDRAM SPECIFICATIONstandard by JEDEC Solid State Technology Association, 02/01/2008

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TESTstandard by JEDEC Solid State Technology Association, 03/01/2009

FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORINGstandard by JEDEC Solid State Technology Association, 04/01/2017

DESCRIPTION OF 1.8 V CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 04/01/2000

2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTSstandard by JEDEC Solid State Technology Association, 06/01/1999

Low Power Double Data Rate 3 SDRAM (LPDDR3)standard by JEDEC Solid State Technology Association, 05/01/2012

PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONSstandard by JEDEC Solid State Technology Association, 03/01/2006

EXTERNAL VISUALstandard by JEDEC Solid State Technology Association, 08/01/2009

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESSstandard by JEDEC Solid State Technology Association, 09/01/2004

LOW POWER DOUBLE DATA RATE 2 (LPDDR2)standard by JEDEC Solid State Technology Association, 12/01/2010

ADDENDUM No. 5 to JESD8 - 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY