INFORMATION REQUIREMENTS FOR THE QUALIFICATION OF SILICON DEVICESstandard by JEDEC Solid State Technology Association, 10/01/2007

STANDARD FOR FAILURE ANALYSIS REPORT FORMATstandard by JEDEC Solid State Technology Association, 12/01/1995

EXTENSION OF THERMAL TEST BOARD STANDARDS FOR PACKAGES WITH DIRECT THERMAL ATTACHMENT MECHANISMSstandard by JEDEC Solid State Technology Association, 02/01/1999

STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) - LEAD (Pb) CONTENTstandard

DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM APPLICATIONSstandard by JEDEC Solid State Technology

IC LATCH-UP TESTstandard by JEDEC Solid State Technology Association, 04/01/2016

Graphics Double Data Rate (GDDR5) SGRAM Standardstandard by JEDEC Solid State Technology Association, 02/01/2016

STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTSstandard by JEDEC Solid State Technology

PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATUREstandard by JEDEC Solid State Technology Association, 10/01/2009

INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINESstandard by JEDEC Solid State Technology Association, 11/01/2006

SON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONSstandard by JEDEC Solid State Technology Association, 07/01/2004

LOW TEMPERATURE STORAGE LIFEstandard by JEDEC Solid State Technology Association, 11/01/2004