TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGESstandard by JEDEC Solid State Technology Association, 10/01/2016

AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUTESstandard by JEDEC Solid State Technology Association, 02/01/2011

ASSESSMENT OF AVERAGE OUTGOING QUALITY LEVELS IN PARTS PER MILLION (PPM)standard by JEDEC Solid State Technology Association, 04/01/1995

SALT ATMOSPHEREstandard by JEDEC Solid State Technology Association, 01/01/2004

Descriptive Designation System for Semiconductor-device Packagesstandard by JEDEC Solid State Technology Association, 04/01/2013

IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)standard by JEDEC Solid State Technology Association, 06/01/2004

ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR

THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)standard by JEDEC Solid State Technology Association, 02/01/1997

Low Power Double Data Rate 3 SDRAM (LPDDR3)standard by JEDEC Solid State Technology Association, 08/01/2015

STATISTICAL PROCESS CONTROL SYSTEMSstandard by JEDEC Solid State Technology Association, 04/01/2015

WIRE BOND SHEAR TESTstandard by JEDEC Solid State Technology Association, 08/01/2009

UNDERSTANDING ELECTRICAL OVERSTRESS - EOSstandard by JEDEC Solid State Technology Association, 09/01/2016