GUIDELINES FOR GaAs MMIC AND FET LIFE TESTINGstandard by JEDEC Solid State Technology Association, 12/01/2018

POWER MOSFET ELECTRICAL DOSE RATE TEST METHODstandard by JEDEC Solid State Technology Association, 08/01/1989

ADDENDUM No. 3A to JESD8 - GUNNING TRANSCEIVER LOGIC (GTL) LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITSstandard by JEDEC Solid State

STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERSFOR REGISTERED DDR2 DIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 01/01/2007

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 09/01/2017

SOLDER BALL PULLstandard by JEDEC Solid State Technology Association, 07/01/2016

FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORINGstandard by JEDEC Solid State Technology Association, 02/01/2007

1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED

COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODESstandard by JEDEC Solid State Technology Association, 05/01/2004

AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUTESstandard by JEDEC Solid State Technology Association, 02/01/2011

ASSESSMENT OF AVERAGE OUTGOING QUALITY LEVELS IN PARTS PER MILLION (PPM)standard by JEDEC Solid State Technology Association, 04/01/1995

SALT ATMOSPHEREstandard by JEDEC Solid State Technology Association, 01/01/2004