GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSISstandard by JEDEC Solid State Technology Association, 09/01/1998

ADDENDUM No. 7 to JESD8 - 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V - 1.95 V (WIDE RANGE) POWER

Low Power Double Data Rate 5 (LPDDR5)standard by JEDEC Solid State Technology Association, 02/01/2019

Overview of Methodologies for the Thermal Measurement of Single- and Multi-Chip, Single- and Multi-PN-Junction Light-Emotting Diodes (LEDs)standard by JEDEC Solid State Technology

TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICESstandard by JEDEC Solid State

CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINEstandard by JEDEC Solid State Technology Association, 03/01/2006

SOLDER BALL SHEARstandard by JEDEC Solid State Technology Association, 10/01/2006

Low Power Double Data Rate 2 (LPDDR2)standard by JEDEC Solid State Technology Association, 04/01/2011

LEADLESS CHIP CARRIER PINOUTS STANDARDIZED FOR LINEARSstandard by JEDEC Solid State Technology Association, 04/01/1982

USER GUIDELINES FOR IR THERMAL IMAGING DETERMINATION OF DIE TEMPERATUREstandard by JEDEC Solid State Technology Association, 09/01/1999

POD135 - 1.35 V Pseudo Open Drain I/Ostandard by JEDEC Solid State Technology Association, 06/01/2019

INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 09/01/2007