Wide I/O Single Data Rate (Wide I/O SDR)standard by JEDEC Solid State Technology Association, 12/01/2011

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICESstandard

METHODS FOR CALCULATING FAILURE RATES IN UNITS OF FITSstandard by JEDEC Solid State Technology Association, 07/01/2001

JOINT JEDEC/ECA STANDARD, DEFINING "LOW-HALOGEN" PASSIVES AND SOLID STATE DEVICES (Removal of BFR/CFR/PVC)standard by JEDEC Solid State Technology Association, 08/01/2011

Handling, Packing, Shipping, and Use of Moisture/Reflow Sensitive Surface-Mount Devicesstandard by JEDEC Solid State Technology Association, 04/01/2018

DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 07/01/2000

EXTERNAL VISUALstandard by JEDEC Solid State Technology Association, 10/01/2015

SEMICONDUCTOR POWER CONTROL MODULESstandard by JEDEC Solid State Technology Association, 11/01/1986

HYBRIDS/MCMstandard by JEDEC Solid State Technology Association, 09/01/2005

SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHODstandard by JEDEC Solid State Technology Association, 02/01/2011

MARK LEGIBILITYstandard by JEDEC Solid State Technology Association, 03/01/2008

ADDENDUM No. 5 to JESD24 - SINGLE PULSE UNCLAMPED INDUCTIVE SWITCHING (UIS) AVALANCHE TEST METHODAmendment by JEDEC Solid State Technology Association, 08/01/1990