STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION)standard by JEDEC Solid State Technology Association, 06/01/2001

GDDR5 SGRAMstandard by JEDEC Solid State Technology Association, 04/01/2013

QUALITY AND RELIABILITY STANDARDS AND PUBLICATIONSstandard by JEDEC Solid State Technology Association, 10/01/1999

TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGESstandard by JEDEC Solid State Technology Association, 09/01/2010

COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 01/01/2003

METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESSstandard by JEDEC Solid State Technology Association, 03/01/2006

MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODESstandard by JEDEC Solid State Technology Association, 07/01/1996

ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHODAmendment by JEDEC Solid State Technology Association, 08/01/1996

PRODUCT DISCONTINUANCEstandard by JEDEC Solid State Technology Association, 05/01/2005

POD10 - 1.0 V Pseudo Open Drain Interfacestandard by JEDEC Solid State Technology Association, 09/01/2011

TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTSstandard by JEDEC Solid State Technology Association, 07/01/2000

Multi-wire Multi-level I/O Standardstandard by JEDEC Solid State Technology Association, 06/01/2016