JEDEC JESD90

JEDEC JESD90

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIESstandard by JEDEC Solid State Technology Association, 11/01/2004

JEDEC JESD8-2

JEDEC JESD8-2

ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITSstandard by

JEDEC JESD 36

JEDEC JESD 36

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 06/01/1996

JEDEC JESD202

JEDEC JESD202

METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESSstandard by JEDEC Solid State Technology Association, 03/01/2006

JEDEC JESD 12-2

JEDEC JESD 12-2

ADDENDUM No. 2 to JESD12 - STANDARD FOR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SETAmendment by JEDEC Solid State Technology Association, 02/01/1986

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