A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIESstandard by JEDEC Solid State Technology Association, 11/01/2004

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONSstandard by JEDEC Solid State Technology Association, 07/01/2001

ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITSstandard by

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MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODESstandard by JEDEC Solid State Technology Association, 07/01/1996

ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHODAmendment by JEDEC Solid State Technology Association, 08/01/1996

PRODUCT DISCONTINUANCEstandard by JEDEC Solid State Technology Association, 05/01/2005

POD10 - 1.0 V Pseudo Open Drain Interfacestandard by JEDEC Solid State Technology Association, 09/01/2011

TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTSstandard by JEDEC Solid State Technology Association, 07/01/2000

COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 01/01/2003

METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESSstandard by JEDEC Solid State Technology Association, 03/01/2006

ADDENDUM No. 2 to JESD12 - STANDARD FOR CELL-BASED INTEGRATED CIRCUIT BENCHMARK SETAmendment by JEDEC Solid State Technology Association, 02/01/1986