STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 06/01/1996

POD125 - 1.25 V PSEUDO OPEN DRAIN I/Ostandard by JEDEC Solid State Technology Association, 09/01/2017

IC LATCH-UP TESTstandard by JEDEC Solid State Technology Association, 12/01/2008

SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERSstandard by JEDEC Solid State Technology Association, 07/01/1996

PRODUCT DISCONTINUANCEstandard by JEDEC Solid State Technology Association, 05/01/2005

POD10 - 1.0 V Pseudo Open Drain Interfacestandard by JEDEC Solid State Technology Association, 09/01/2011

TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTSstandard by JEDEC Solid State Technology Association, 07/01/2000

COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 01/01/2003

METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESSstandard by JEDEC Solid State Technology Association, 03/01/2006

MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODESstandard by JEDEC Solid State Technology Association, 07/01/1996

ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHODAmendment by JEDEC Solid State Technology Association, 08/01/1996

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 02/01/2011