JEDEC JESD82-3B

JEDEC JESD82-3B

DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 11/01/2004

JEDEC JESD217

JEDEC JESD217

TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGESstandard by JEDEC Solid State Technology Association, 09/01/2010

JEDEC JESD90

JEDEC JESD90

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIESstandard by JEDEC Solid State Technology Association, 11/01/2004

JEDEC JESD8-2

JEDEC JESD8-2

ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITSstandard by

JEDEC JESD 36

JEDEC JESD 36

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 06/01/1996

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