JEDEC JESD79-4-1
Addendum No. 1 to JESD79-4, 3D Stacked DRAM StandardAmendment by JEDEC Solid State Technology Association, 02/01/2017
Addendum No. 1 to JESD79-4, 3D Stacked DRAM StandardAmendment by JEDEC Solid State Technology Association, 02/01/2017
TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN INTEGRATED CIRCUITSstandard by JEDEC Solid State
NAND Flash Interface Interoperabilitystandard by JEDEC Solid State Technology Association, 07/01/2014
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)standard by JEDEC Solid State Technology Association, 11/01/2010
QUALITY AND RELIABILITY STANDARDS AND PUBLICATIONSstandard by JEDEC Solid State Technology Association, 10/01/1999
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGESstandard by JEDEC Solid State Technology Association, 09/01/2010
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIESstandard by JEDEC Solid State Technology Association, 11/01/2004
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONSstandard by JEDEC Solid State Technology Association, 07/01/2001
ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITSstandard by
STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 06/01/1996
POD125 - 1.25 V PSEUDO OPEN DRAIN I/Ostandard by JEDEC Solid State Technology Association, 09/01/2017