JEDEC JEP 122E
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 03/01/2009
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 03/01/2009
STANDARD FOR THE MEASUREMENT OF CREstandard by JEDEC Solid State Technology Association, 11/01/1967
Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, and DDR3L-1600Amendment by JEDEC Solid State Technology Association, 01/01/2013
RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICESstandard by JEDEC Solid State Technology Association, 04/01/2008
POD125 - 1.25 V Pseudo Open Drain I/Ostandard by JEDEC Solid State Technology Association, 06/01/2019
DESCRIPTION OF 5 V BUS SWITCH WITH TTL-COMPATIBLE CONTROL INPUTSstandard by JEDEC Solid State Technology Association, 06/01/1999
BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICS FOR HANDHELD ELECTRONIC PRODUCTSstandard by JEDEC Solid State Technology
TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENTstandard by JEDEC Solid State Technology Association, 06/01/2001
REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICESstandard by JEDEC Solid State Technology Association, 01/01/2012
HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODTstandard by JEDEC Solid State Technology Association, 04/01/2014
ELECTROSTATIC DISCHARGE SENSITIVITY TESTING, HUMAN BODY MODEL (HBM) - COMPONENT LEVELstandard by JEDEC Solid State Technology Association, 04/01/2010
RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENTstandard by JEDEC Solid State Technology Association, 01/01/2014