JEDEC JESD22-A111A

JEDEC JESD22-A111A

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICESstandard

JEDEC J-STD-609B

JEDEC J-STD-609B

MARKING, SYMBOLS, AND LABELS OF LEADED AND LEAD-FREE TERMINAL FINISHED MATERIALS USED IN ELECTRONIC ASSEMBLYstandard by JEDEC Solid State Technology Association, 04/01/2016

JEDEC JESD51-3

JEDEC JESD51-3

LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGESstandard by JEDEC Solid State Technology Association, 08/01/1996

JEDEC JESD82-8.01

JEDEC JESD82-8.01

STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 02/01/2004

JEDEC JESD241

JEDEC JESD241

Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilitiesstandard by JEDEC Solid State Technology Association, 12/01/2015

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