Mechanical Shock - Component and Subassemblystandard by JEDEC Solid State Technology Association, 07/01/2013

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICESstandard

LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGESstandard by JEDEC Solid State Technology Association, 08/01/1996

STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 02/01/2004

STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION)standard by JEDEC Solid State Technology Association, 06/01/2001

SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTIONstandard by JEDEC Solid State Technology Association, 03/01/2011

MARKING PERMANENCYstandard by JEDEC Solid State Technology Association, 03/01/2011

Alpha Radiation Measurement in Electronic Materialsstandard by JEDEC Solid State Technology Association, 05/01/2011

Low Power Double Data Rate 2 (LPDDR2)standard by JEDEC Solid State Technology Association, 06/01/2013

Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilitiesstandard by JEDEC Solid State Technology Association, 12/01/2015

PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICSstandard by JEDEC Solid State Technology Association, 03/01/2010

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 03/01/2009