A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESSstandard by JEDEC Solid State Technology Association, 12/01/2001

STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCHstandard by JEDEC Solid State Technology Association, 11/01/2001

Universal Flash Storage (UFS)standard by JEDEC Solid State Technology Association, 06/01/2012

Graphics Double Data Rate (GDDR5) SGRAM Standardstandard by JEDEC Solid State Technology Association, 12/01/2013

THERMAL SHOCKstandard by JEDEC Solid State Technology Association, 06/01/2004

TEST METHODS AND ACCEPTANCE PROCEDURES FOR THE EVALUATION OF POLYMERIC MATERIALSstandard by JEDEC Solid State Technology Association, 06/01/2001

UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 10/01/2009

AVALANCHE BREAKDOWN DIODE (ABD) TRANSIENT VOLTAGE SUPPRESSORSstandard by JEDEC Solid State Technology Association, 03/01/2017

INDEX OF TERMS DEFINED IN JEDEC PUBLICATIONSstandard by JEDEC Solid State Technology Association, 05/01/2000

HIGH TEMPERATURE STORAGE LIFEstandard by JEDEC Solid State Technology Association, 10/01/2015

Mechanical Shock - Component and Subassemblystandard by JEDEC Solid State Technology Association, 07/01/2013

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICESstandard