METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITSstandard by JEDEC Solid State Technology Association, 01/01/1970

GUIDELINES FOR PARTICLE IMPACT NOISE DETECTION (PIND) TESTING, OPERATOR TRAINING, AND CERTIFICATIONstandard by JEDEC Solid State Technology Association, 10/01/2007

GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTINGstandard by JEDEC Solid State Technology Association, 11/01/1996

Failure Mechanisms and Models for Semiconductor Devicesstandard by JEDEC Solid State Technology Association, 09/01/2016

A PROCEDURE FOR EXECUTING SWEATstandard by JEDEC Solid State Technology Association, 08/01/2003

RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENTstandard by JEDEC Solid State Technology Association, 12/01/2008

Long-Term Storage for Electronic Solid-State Wafers, Dice, and Devicesstandard by JEDEC Solid State Technology Association, 11/01/2011

SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIESstandard by JEDEC Solid State Technology Association, 07/01/2012

Guide to Standards and Publications Relating to Quality and Reliability of Electronic Hardwarestandard by JEDEC Solid State Technology Association, 10/01/2013

, Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devicesstandard by JEDEC Solid State Technology

ADDENDUM No. 1 TO EIA-397Amendment by JEDEC Solid State Technology Association, 07/01/1980

ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL STANDARDAmendment by JEDEC Solid State Technology Association, 06/01/1986