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This standard provides a chip carrier format for digital devices by defining pin functions and locations for 20, 38, 44, 52, and 68-terminal devices.
Failure Mechanisms and Models for Semiconductor Devicesstandard by JEDEC Solid State Technology Association, 09/01/2016
METHODS OF MEASUREMENT FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITSstandard by JEDEC Solid State Technology Association, 01/01/1970
GUIDELINES FOR PARTICLE IMPACT NOISE DETECTION (PIND) TESTING, OPERATOR TRAINING, AND CERTIFICATIONstandard by JEDEC Solid State Technology Association, 10/01/2007
GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTINGstandard by JEDEC Solid State Technology Association, 11/01/1996